switching and improved dynamic threshold performance.
錚?/div>
output control and
undershoot corrector in addition to a split ground bus for
superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
Faster prop delays than the standard AC
Ordering Code:
Order Number
74ACQ241SC
74ACQ241PC
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
鈥揑
7
O
0
鈥揙
7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
Truth Tables
Inputs
OE
1
I
n
L
H
X
Inputs
OE
2
H
H
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Outputs
(Pins 12, 14, 16, 18)
L
H
Z
Outputs
I
n
L
H
X
X
=
Immaterial
Z
=
High Impedance
Connection Diagram
L
L
H
(Pins 3, 5, 7, 9)
L
H
Z
FACT錚? FACT Quiet Series錚? and GTO錚?are trademarks of Fairchild Semiconductor Corporation.
漏 2001 Fairchild Semiconductor Corporation
DS010642
www.fairchildsemi.com