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74AC574M Datasheet

  • 74AC574M

  • Octal D-Type Flip-Flop

  • 11頁

  • ETC

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74AC574
OCTAL D-TYPE FLIP-FLOP
WITH 3 STATE OUTPUTS (NON INVERTED)
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 250MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4碌A(MAX.) at T
A
=25擄C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
50鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC574B
74AC574M
T&R
74AC574MTR
74AC574TTR
DESCRIPTION
The 74AC574 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP-FLOP with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type Flip-Flop are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic that were setup at
the D inputs.
PIN CONNECTION AND IEC LOGIC SYMBOLS
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level); while
OE is in high level, the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
April 2001
1/11

74AC574M 產(chǎn)品屬性

  • STMicroelectronics

  • 觸發(fā)器

  • 8

  • 74AC

  • D-Type Flip-Flop

  • Non-Inverting

  • Single-Ended

  • Single-Ended

  • 13.5 ns

  • - 24 mA

  • 24 mA

  • 6 V

  • + 125 C

  • SMD/SMT

  • SOP-20

  • Tube

  • - 55 C

  • 8

  • 3

  • 40

  • 2 V

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