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74AC573M Datasheet

  • 74AC573M

  • OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

  • 10頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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74AC573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4.5 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 8
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
50鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
IMPROVED LATCH-UP IMMUNITY
M
B
(Plastic Package)
(Micro Package)
ORDER CODES :
74AC573B
74AC573M
latch enable input (LE) and an output enable
input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The AC573 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power applications
mantaining high speed operation similar to
equivalent Bipolar Schottky TTL.
These 8 bit D-Type latches are controlled by a
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
1/10

74AC573M 產(chǎn)品屬性

  • STMicroelectronics

  • 閉鎖

  • 8

  • D-Type Latch

  • 74AC

  • Non-Inverting

  • 3

  • - 24 mA

  • 32 mA

  • 13 ns at 3.3 V, 10 ns at 5 V

  • 6 V

  • 2 V

  • + 125 C

  • - 55 C

  • SOP-20

  • Tube

  • SMD/SMT

  • 8

  • 40

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