74AC299 鈥?74ACT299 8-Input Universal Shift/Storage Register
July 1988
Revised March 2005
74AC299 鈥?74ACT299
8-Input Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The AC/ACT299 is an 8-bit universal shift/storage register
with 3-STATE outputs. Four modes of operation are possi-
ble: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Additional out-
puts are provided for flip-flops Q
0
, Q
7
to allow easy serial
cascading. A separate active LOW Master Reset is used to
reset the register.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Common parallel I/O for reduced pin count
s
Additional serial inputs and outputs for expansion
s
Four operating modes: shift left, shift right, load
and store
s
3-STATE outputs for bus-oriented applications
s
Outputs source/sink 24 mA
s
ACT299 has TTL-compatible inputs
Ordering Code:
Order Number
74AC299SC
74AC299SCX_NL
(Note 1)
74AC299SJ
74AC299MTC
74AC299PC
74ACT299SC
74ACT299MTC
74ACT299PC
Package Number
M20B
M20B
M20D
MTC20
N20A
M20B
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
CP
DS
0
DS
7
S
0
, S
1
MR
OE
1
, OE
2
I/O
0
鈥揑/O
7
Q
0
, Q
7
Description
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
3-STATE Output Enable Inputs
Parallel Data Inputs or
3-STATE Parallel Outputs
Serial Outputs
FACT
樓
is a trademark of Fairchild Semiconductor Corporation.
漏 2005 Fairchild Semiconductor Corporation
DS009893
www.fairchildsemi.com
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