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74AC280MTR Datasheet

  • 74AC280MTR

  • Parity Generator/Checker

  • 10頁

  • ETC

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74AC280
9 BIT PARITY GENERATOR
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 6ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4碌A(chǔ)(MAX.) at T
A
=25擄C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
50鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC280B
74AC280M
T&R
74AC280MTR
74AC280TTR
DESCRIPTION
The 74AC280 is an advanced high-speed CMOS
9 BIT PARITY GENERATOR fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS tecnology.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (危ODD and
危EVEN).
The nine
data inputs control the output conditions. When
the number of high level input is odd,
危ODD
output is kept high and
危EVEN
output low.
Conservely, when the output is even,
危EVEN
output is kept high and
危ODD
low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easly expanded by cascading.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/10

74AC280MTR 產(chǎn)品屬性

  • STMicroelectronics

  • 奇偶功能

  • 1

  • 9

  • AC

  • SO-14

  • - 24 mA

  • 24 mA

  • 17 ns, 13 ns

  • 2.5 V, 3.3 V, 5 V

  • + 125 C

  • - 55 C

  • Reel

  • SMD/SMT

  • 2500

  • 6 V

  • 2 V

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