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74AC280 Datasheet

  • 74AC280

  • 9 BIT PARITY GENERATOR

  • 8頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74AC280
9 BIT PARITY GENERATOR
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
50鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
IMPROVED LATCH-UP IMMUNITY
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74AC280B
74AC280M
odd/even parity outputs (
危
ODD and
危
EVEN). The
nine data inputs control the output conditions.
When the number of high level input is odd,
危
ODD output is kept high and
危
EVEN output low.
Conservely, when the output is even,
危EVEN
output is kept high and
危ODD
low.
The IC generates either odd or even parity
making it flexible application.
The word-length capability is easily expanded by
cascading.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The AC280 is an advanced high-speed CMOS 9
BIT PARITY GENERATOR fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to equivalent Bipolar Schottky
TTL.
It is composed of nine data inputs (A to I) and
PIN CONNECTION AND IEC LOGIC SYMBOLS
December 1998
1/8

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