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74AC273MTC Datasheet

  • 74AC273MTC

  • Octal D-Type Flip-Flop

  • 10頁

  • FAIRCHILD

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74AC273 鈥?74ACT273 Octal D-Type Flip-Flop
November 1988
Revised August 2000
74AC273 鈥?74ACT273
Octal D-Type Flip-Flop
General Description
The AC273 and ACT273 have eight edge-triggered D-type
flip-flops with individual D-type inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (MR) input
load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop鈥檚 Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s
Ideal buffer for microprocessor or memory
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
Buffered, asynchronous master reset
s
See 377 for clock enable version
s
See 373 for transparent latch version
s
See 374 for 3-STATE version
s
Outputs source/sink 24 mA
s
74ACT273 has TTL-compatible inputs
Ordering Code:
Order Number
74AC273SC
74AC273SJ
74AC273MTC
74AC273PC
74ACT273SC
74ACT273SJ
74ACT273MTC
74ACT273PC
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
FACT錚?is a trademark of Fairchild Semiconductor Corporation.
漏 2000 Fairchild Semiconductor Corporation
DS009954
www.fairchildsemi.com

74AC273MTC 產(chǎn)品屬性

  • 1,825

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74AC

  • 主復(fù)位

  • D 型總線

  • 非反相

  • 1

  • 8

  • 175MHz

  • 5.5ns

  • 正邊沿

  • 24mA，24mA

  • 2 V ~ 6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-TSSOP（0.173"，4.40mm 寬）

  • 管件

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