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74AC138M Datasheet

  • 74AC138M

  • 3 TO 8 LINE DECODER INVERTING

  • 278.34KB

  • 10頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74AC138
3 TO 8 LINE DECODER (INVERTING)
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4.5ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4碌A(chǔ)(MAX.) at T
A
=25擄C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
50鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC138B
74AC138M
T&R
74AC138MTR
74AC138TTR
DESCRIPTION
The 74AC138 is an advanced high-speed CMOS
3 TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS tecnology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/10

74AC138M 產(chǎn)品屬性

  • STMicroelectronics

  • 編碼器、解碼器、復(fù)用器和解復(fù)用器

  • Decoder / Demultiplexer

  • 74AC

  • 3 / 8

  • 6 V

  • 2 V

  • + 85 C

  • SMD/SMT

  • SOP-16

  • Tube

  • - 40 C

  • 3

  • 8

  • 50

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