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(Enhanced-Performance Implanted
CMOS) 1-碌m Process
Package Options Include Plastic
Small-Outline Packages, and Standard
Plastic 300-mil DIPs
D OR N PACKAGE
(TOP VIEW)
A
B
1Y
GND
2Y
1OE
2OE
2C3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1C0
1C1
1C2
1C3
V
CC
2C0
2C1
2C2
description
Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data
selection to the AND-OR gates. Separate strobe output-enable (1OE or 2OE) inputs are provided for each of
the two four-line sections.
The 3-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high-impedance state), the low impedance of the single enabled output will drive
the bus line to a high or low logic level. Each output has its own strobe. The output is disabled when its strobe
is high.
The 74AC11353 is characterized for operation from 鈥?40擄C to 85擄C.
FUNCTION TABLE
SELECT
INPUTS
B
X
L
L
L
L
H
H
H
H
A
X
L
L
H
H
L
L
H
H
C0
X
L
H
X
X
X
X
X
X
DATA INPUTS
C1
X
X
X
L
H
X
X
X
X
C2
X
X
X
X
X
L
H
X
X
C3
X
X
X
X
X
X
X
L
H
STROBE
OE
H
L
L
L
L
L
L
L
L
OUTPUT
Y
Z
H
L
H
L
H
L
H
L
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1993, Texas Instruments Incorporated
Revision Information
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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