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74AC11174 Datasheet

  • 74AC11174

  • HEX D-TYPE FLIP-FLOP WITH CLEAR

  • 7頁

  • TI

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74AC11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 鈥?MARCH 1990 鈥?REVISED APRIL 1993
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Pin Configurations
Minimize High-Speed Switching Noise
EPIC
鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
500-mA Typical Latch-Up Immunity at 125擄C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
DW OR N PACKAGE
(TOP VIEW)
1Q
2Q
3Q
GND
GND
GND
GND
4Q
5Q
6Q
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1D
2D
3D
V
CC
V
CC
4D
5D
6D
CLK
description
This device contains six D-type flip-flops and is positive-edge-triggered with a direct clear input. Information at
the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time
of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect
at the output.
The 74AC11174 is characterized for operation from 鈥?40擄C to 85擄C.
FUNCTION TABLE
INPUTS
CLR
L
H
H
H
CLK
X
鈫?/div>
鈫?/div>
L
D
X
H
L
X
OUTPUT
Q
L
H
L
QO
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
2鈥?

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