鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
500-mA Typical Latch-Up Immunity at
125擄C
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
D, N, OR PW PACKAGE
(TOP VIEW)
1Y1
1Y2
1Y3
GND
2Y0
2Y1
2Y2
2Y3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1Y0
1A
1B
1G
V
CC
2G
2A
2B
description
The 74AC11139 circuit is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. In high-performance memory systems, this decoder
can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing
a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than
the typical access time of the memory. This means that the effective system delay introduced by the decoder
is negligible.
The 74AC11139 is composed of two individual 2-line to 4-line decoders in a single package. The active-low
enable input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully
buffered inputs, each of which represents only one normalized load to its driving circuit.
The 74AC11139 is characterized for operation from 鈥?0擄C to 85擄C.
FUNCTION TABLE
ENABLE
INPUT
G
H
L
L
L
L
SELECT
INPUTS
A
X
L
H
L
H
B
X
L
L
H
H
Y0
H
L
H
H
H
OUTPUTS
Y1
H
H
L
H
H
Y2
H
H
H
L
H
Y3
H
H
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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