鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
500-mA Typical Latch-Up Immunity at
125擄C
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
D, N, OR PW PACKAGE
(TOP VIEW)
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLK
1D
1CLR
V
CC
2CLR
2D
2CLK
description
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)
or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the
outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is
not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may
be changed without affecting the levels at the outputs.
The 74AC11074 is characterized for operation from 鈥?0擄C to 85擄C.
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
D
X
X
X
H
L
X
OUTPUT
Q
H
L
H鈥?/div>
H
L
Q0
Q
L
H
H鈥?/div>
L
H
Q0
擄
擄
L
鈥?This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1
1
2
3
4
5
6
