鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
500-mA Typical Latch-Up Immunity at
125擄C
Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic 300-mil DIPs (N)
D OR N PACKAGE
(TOP VIEW)
description
1A
1Y
2Y
GND
GND
3Y
4Y
4B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
2A
2B
V
CC
V
CC
3A
3B
4A
This device contains four independent 2-input NAND gates. It performs the Boolean function Y = A
Y = A + B in positive logic.
The 74AC11000 is characterized for operation from 鈥?0擄C to 85擄C.
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
S
B or
logic symbol
鈥?/div>
1A
1B
2A
2B
3A
3B
4A
4B
1
16
15
14
11
10
9
8
7
4Y
6
3Y
3
2Y
&
2
1Y
鈥?This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1
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