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74ABT544D Datasheet

  • 74ABT544D

  • Octal latched transceiver with dual enable, inverting 3-Stat...

  • 8頁(yè)

  • PHILIPS

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Philips Semiconductors Advanced BiCMOS Products
Product specification
Octal latched transceiver with dual enable,
inverting (3-State)
鈥?/div>
ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
Machine Model
74ABT544
FEATURES
鈥?/div>
Combines 74ABT245 and 74ABT373 type
functions in one device
FUNCTIONAL DESCRIPTION
The 鈥橝BT544 contains two sets of eight
D鈥搕ype latches, with separate control pins for
each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB)
input and the A-to-B Latch Enable (LEAB)
input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the
LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer
change with the A inputs. With EAB and
OEAB both Low, the 3-State B output buffers
are active and invert the data present at the
outputs of the A latches.
Control of data flow from B to A is similar, but
using the EBA, LEBA, and OEBA inputs.
鈥?/div>
8-bit octal transceiver with D-type latch
鈥?/div>
Back-to-back registers for storage
鈥?/div>
Separate controls for data flow in each
direction
DESCRIPTION
The 74ABT544 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The 74ABT544 Octal Registered Transceiver
contains two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB,
LEBA) and Output Enable (OEAB, OEBA)
inputs are provided for each register to
permit independent control of data transfer in
either direction. The outputs are guaranteed
to sink 64mA.
鈥?/div>
Output capability: +64mA/鈥?2mA
鈥?/div>
Live insertion/extraction permitted
鈥?/div>
Power-up 3-State
鈥?/div>
Power-up reset
鈥?/div>
Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
ORDERING INFORMATION
PACKAGES
24-pin plastic DIP
24-pin plastic SOL
24-pin plastic SSOP Type II
TEMPERATURE RANGE
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
ORDER CODE
74ABT544N
74ABT544D
74ABT544DB
DRAWING NUMBER
0410D
0173D
1641A
PIN CONFIGURATION
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
2
23
1EN3 (AB)
G1
1C5
2EN4 (BA)
G2
2C6
22
5D
鈭?/div>
4
21
20
19
18
17
16
15
LEBA
OEBA
1
2
24 V
CC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
11
23
A0 A1 A2 A3 A4 A5 A6 A7
EAB
EBA
LEAB
LEBA
B0 B1 B2 B3 B4 B5 B6 B7
OEAB
OEBA
13
2
3
4
5
6
7
8
9
10
1
13
11
14
A0 3
A1 4
A2
A3
5
6
3
4
鈭?/div>
3
5D
A4 7
A5 8
A6
9
14
1
5
6
7
8
A7 10
EAB 11
GND 12
14 LEAB
13 OEAB
22 21 20 19 18 17 16 15
9
10
June 1, 1993
1
853鈥?610 09907

74ABT544D 產(chǎn)品屬性

  • NXP

  • 總線收發(fā)器

  • BiCMOS

  • ABT

  • 8

  • TTL

  • TTL

  • 3-State

  • - 32 mA

  • 64 mA

  • 4.5 ns

  • 5.5 V

  • 4.5 V

  • + 85 C

  • SO-24

  • Tube

  • Latched Transceiver

  • - 40 C

  • SMD/SMT

  • 1

  • Inverting

  • 30

  • 74ABT544D,602

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