鈥?/div>
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
SA00001
PIN DESCRIPTION
PIN NUMBER
2, 12
3, 11
4, 10
1, 13
5, 9
6, 8
7
14
SYMBOL
D0, D1
CP0, CP1
SD0, SD1
RD0, RD1
Q0, Q1
Q0, Q1
GND
V
CC
NAME AND FUNCTION
Data inputs
Clock inputs (active rising edge)
Set inputs (active-Low)
Reset inputs (active-Low)
Data outputs (active-Low),
non-inverting
Data outputs (active-Low),
inverting
Ground (0V)
Positive supply voltage
DESCRIPTION
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. Data must be stable
just one setup time prior to the low-to-high transition of the clock for
guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive-going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
The 74ABT5074 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the
74ABT5074 are:
蟿 鈮?/div>
94ps and T
o
鈮?/div>
1.3
脳
10
7
sec
where
蟿
represents a function of the rate at which a latch in a
metastable state resolves that condition and T
0
represents a
function of the measurement of the propensity of a latch to enter a
metastable state.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
I
CC
PARAMETER
Propagation delay
CPn to Qn or Qn
Input capacitance
Total supply current
CONDITIONS
T
amb
= 25擄C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
2.8
2.4
3
2
UNIT
ns
pF
碌A(chǔ)
ORDERING INFORMATION
PACKAGES
14-pin plastic DIP
14-pin plastic SOL
14-pin plastic shrink small outline SSOP Type II
14-pin plastic thin shrink small outline (TSSOP) Type I
TEMPERATURE RANGE
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
ORDER CODE
74ABT5074N
74ABT5074D
74ABT5074DB
74ABT5074PW
DRAWING NUMBER
SOT27-1
SOT108-1
SOT337-1
SOT402-1
December 15, 1994
1
853-1775 14470
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