74ABT125 Quad Buffer with 3-STATE Outputs
March 1994
Revised February 2005
74ABT125
Quad Buffer with 3-STATE Outputs
General Description
The ABT125 contains four independent non-inverting buff-
ers with 3-STATE outputs.
Features
s
Non-inverting buffers
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
s
Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number
74ABT125CSC
74ABT125CSJ
74ABT125CMTC
74ABT125CMTCX_NL
(Note 1)
Package
Number
M14A
M14D
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
A
n
, B
n
O
n
Descriptions
Inputs
Outputs
Function Table
Inputs
A
n
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
Z HIGH Impedance
X Immaterial
Output
B
n
L
H
X
O
n
L
H
Z
漏 2005 Fairchild Semiconductor Corporation
DS011667
www.fairchildsemi.com