54LS164 DM54LS164 DM74LS164 8-Bit Serial In Parallel Out Shift Registers
June 1989
54LS164 DM54LS164 DM74LS164
8-Bit Serial In Parallel Out Shift Registers
General Description
These 8-bit shift registers feature gated serial inputs and an
asynchronous clear A low logic level at either input inhibits
entry of the new data and resets the first flip-flop to the low
level at the next clock pulse thus providing complete con-
trol over incoming data A high logic level on either input
enables the other input which will then determine the state
of the first flip-flop Data at the serial inputs may be changed
while the clock is high or low but only information meeting
the setup and hold time requirements will be entered Clock-
ing occurs on the low-to-high level transition of the clock
input All inputs are diode-clamped to minimize transmis-
sion-line effects
Features
Y
Y
Y
Y
Y
Y
Gated (enable disable) serial inputs
Fully buffered clock and serial inputs
Asynchronous clear
Typical clock frequency 36 MHz
Typical power dissipation 80 mW
Alternate Military Aerospace device (54LS164) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram
Dual-In-Line Package
Function Table
Inputs
Clear
L
H
H
H
H
Clock
X
L
A
X
X
H
L
X
B
X
X
H
X
L
Q
A
L
Q
A0
H
L
L
Outputs
Q
B
L
Q
B0
Q
An
Q
An
Q
An
Q
H
L
Q
H0
Q
Gn
Q
Gn
Q
Gn
u
u
u
H
e
High Level (steady state) L
e
Low Level (steady state)
X
e
Don鈥檛 Care (any input including transitions)
u
e
Transition from low to high level
Q
A0
Q
B0
Q
H0
e
The level of Q
A
Q
B
or Q
H
respectively before the
indicated steady-state input conditions were established
Q
An
Q
Gn
e
The level of Q
A
or Q
G
before the most recent
the clock indicates a one-bit shift
u
transition of
TL F 6398 鈥?1
Order Number 54LS164DMQB 54LS164FMQB
54LS164LMQB DM54LS164J DM54LS164W
DM74LS164M or DM74LS164N
See NS Package Number E20A
J14A M14A N14A or W14B
Logic Diagram
TL F 6398 鈥?2
C
1995 National Semiconductor Corporation
TL F 6398
RRD-B30M105 Printed in U S A
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