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54F825SDM Datasheet

  • 54F825SDM

  • 8-Bit D-Type Flip-Flop

  • 8頁

  • NSC

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54F 74F825 8-Bit D-Type Flip-Flop
December 1994
54F 74F825
8-Bit D-Type Flip-Flop
General Description
The 鈥橣825 is an 8-bit buffered register It has Clock Enable
and Clear features which are ideal for parity bus interfacing
in high performance microprogramming systems Also in-
cluded in the 鈥橣825 are multiple enables that allow multi-
user control of the interface
The 鈥橣825 is functionally and pin compatible with AMD鈥檚
Am29825
Features
Y
Y
Y
Y
TRI-STATE output
Clock enable and clear
Multiple output enables
Direct replacement for AMD鈥檚 Am24825
Commercial
74F825SPC
Military
Package
Number
N24C
Package Description
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead Cerpack
24-Lead Ceramic Leadless Chip Carrier Type C
54F825SDM (Note 2)
74F825SC (Note 1)
54F825FM (Note 2)
54F825LM (Note 2)
Note 1
Devices also available in 13 reel Use suffix
e
SCX
J24F
M24B
W24C
E28A
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
SDMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9597 鈥?1
TL F 9597 鈥?4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9597
RRD-B30M75 Printed in U S A

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