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54ACTQ841 Datasheet

  • 54ACTQ841

  • Quiet Series 10-Bit Transparent Latch with TRI-STATE Outputs

  • 8頁

  • NSC

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54ACTQ841 Quiet Series 10-Bit Transparent Latch with TRI-STATE Outputs
August 1998
54ACTQ841
Quiet Series 10-Bit Transparent Latch with TRI-STATE
廬
Outputs
General Description
The 鈥橝CTQ841 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The 鈥?41 is a 10-bit transparent latch,
a 10-bit version of the 鈥?73. The 鈥橝CTQ841 utilizes NSC
Quiet Series technology to guarantee quiet output switching
and improved dynamic threshold performance, FACT Quiet
Series
鈩?/div>
features GTO
鈩?/div>
output control and undershoot cor-
rector in addition to a split ground bus for superior perfor-
mance.
Features
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n
Improved latch-up immunity
n
Outputs source/sink 24 mA
n
鈥橝CTQ841 has TTL-compatible inputs
n
Standard Microcircuit Drawing (SMD) 5962-92200
Logic Symbols
DS100250-1
DS100250-2
Pin Names
D
0
鈥揇
9
O
0
鈥揙
9
OE
LE
Description
Data Inputs
TRI-STATE Outputs
Output Enable
Latch Enable
GTO
鈩?/div>
is a trademark of National Semiconductor Corporation.
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
鈩?/div>
is a trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100250
www.national.com

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