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54ACTQ533D Datasheet

  • 54ACTQ533D

  • Quiet Series Octal Transparent Latch with TRI-STATE Outputs

  • 8頁(yè)

  • NSC

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54ACTQ533 Quiet Series Octal Transparent Latch with TRI-STATE Outputs
August 1998
54ACTQ533
Quiet Series Octal Transparent Latch with TRI-STATE
廬
Outputs
General Description
The ACTQ533 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The flip-flops ap-
pear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing re-
quirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus out-
put is in the high impedance state.
The ACTQ533 utilizes NSC Quiet Series technology to guar-
antee quiet output switching and improve dynamic threshold
performance. FACT Quiet Series
鈩?/div>
features GTO
鈩?/div>
output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Features
n
I
CC
and I
OZ
reduced by 50%
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch up immunity
n
Eight latches in a single package
n
TRI-STATE outputs drive bus lines or buffer memory
address registers
n
Outputs source/sink 24 mA
n
Inverted version of the ACTQ373
n
4 kV minimum ESD immunity
Logic Symbols
IEEE/IEC
DS100241-1
DS100241-2
Pin
Names
D
0
鈥揇
7
LE
OE
O
0
鈥揙
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch
Outputs
GTO
鈩?/div>
is a trademark of National Semiconductor Corporation.
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
鈩?/div>
is a trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100241
www.national.com

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