鈩?/div>
output control and undershoot corrector in addition to
a split ground bus for superior performance.
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch-up immunity
n
TRI-STATE outputs drive bus lines or buffer memory
address registers
n
Outputs source/sink 24 mA
n
Faster prop delays than the standard 鈥橝C/鈥橝CT241
n
4 kV minimum ESD immunity (鈥橝CTQ)
n
Standard Microcircuit Drawing (SMD) 5962-92185
Features
n
I
CC
and I
OZ
reduced by 50%
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100246-2
DS100246-1
Pin Names
OE
1
, OE
2
I
0
鈥揑
7
O
0
鈥揙
7
Inputs
Outputs
Description
TRI-STATE Output Enable Inputs
Pin Assignment
for LCC
DS100246-3
GTO
鈩?/div>
is a trademark of National Semiconductor Corporation.
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
鈩?/div>
is a trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100246
www.national.com
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