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54ACT74L Datasheet

  • 54ACT74L

  • Dual D-Type Positive Edge-Triggered Flip-Flop

  • 171.73KB

  • 8頁(yè)

  • NSC

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54AC74
鈥?/div>
54ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
August 1998
54AC74
鈥?/div>
54ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The 鈥橝C/鈥橝CT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs. In-
formation at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to
the transition time of the positive-going pulse. After the Clock
Pulse input threshold voltage has been passed, the Data in-
put is locked out and information present will not be trans-
ferred to the outputs until the next rising edge of the Clock
Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n
n
n
n
I
CC
reduced by 50%
Output source/sink 24 mA
鈥橝CT74 has TTL-compatible inputs
Standard Microcircuit Drawing (SMD)
鈥?鈥橝C74: 5962-88520
鈥?鈥橝CT74: 5962-87525
Logic Symbols
DS100266-2
DS100266-1
Pin Names
IEEE/IEC
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
DS100266-3
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100266
www.national.com

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