鈩?/div>
output control and un-
dershoot corrector in addition to a split ground bus for supe-
rior performance.
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch-up immunity
n
Inverting TRI-STATE outputs drive bus lines or buffer
memory address registers
n
Outputs source/sink 24 mA
n
Faster prop delays than the standard 鈥橝CT240
n
4 kV minimum ESD immunity
n
Standard Microcircuit Drawing (SMD)
鈥橝CTQ240: 5962-92184
Features
n
I
CC
and I
OZ
reduced by 50%
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100235-1
DS100235-2
Pin Names
OE
1
, OE
2
I
0
鈥揑
7
O
0
鈥揙
7
Inputs
Outputs
Description
TRI-STATE Output Enable Inputs
Pin Assignment
for LCC
DS100235-3
GTO
鈩?/div>
is a trademark of National Semiconductor Corporation.
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
鈩?/div>
is a trademark of Fairchild Semiconductor Corporation.
漏 1999 National Semiconductor Corporation
DS100235
www.national.com
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