54AC280 9-Bit Parity Generator/Checker
September 1998
54AC280
9-Bit Parity Generator/Checker
General Description
The 鈥橝C280 is a high-speed parity generator/checker that
accepts nine bits of input data and detects whether an even
or an odd number of these inputs is HIGH. If an even number
of inputs is HIGH, the Sum Even output is HIGH. If an odd
number is HIGH, the Sum Even output is LOW. The Sum
Odd output is the complement of the Sum Even output.
Features
n
I
CC
reduced by 50%
n
9-bit width for memory applications
n
Standard Microcircuit Drawing (SMD) 5962-92201
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP and Flatpak
DS100359-1
IEEE/IEC
DS100359-2
Pin Assignment for LCC
DS100359-4
Pin
Names
I
0
鈥揑
8
鈭?/div>
O
鈭?/div>
E
Description
DS100359-3
Data Inputs
Odd Parity Output
Even Parity Output
Truth Table
Number of
HIGH Inputs
I
0
鈥揑
8
0, 2, 4, 6, 8
1, 3, 5, 7, 9
H = HIGH Voltage Level
L = LOW Voltage Level
Outputs
鈭?/div>
Even
鈭?/div>
Odd
H
L
L
H
FACT
鈩?/div>
is a trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100359
www.national.com
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