54AC163L Datasheet

IC型號(hào)：
54AC163L
PDF描述：
Synchronous Presettable Binary Counter
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194.06KB
PDF頁(yè)數(shù)：
12頁(yè)
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54AC163

鈥?/div>

54ACT163 Synchronous Presettable Binary Counter

November 1998

54AC163

鈥?/div>

54ACT163

Synchronous Presettable Binary Counter

General Description

The 鈥橝C/鈥橝CT163 are high-speed synchronous modulo-16

binary counters. They are synchronously presettable for ap-

plication in programmable dividers and have two types of

Count Enable inputs plus a Terminal Count output for versa-

tility in forming synchronous multistage counters. The 鈥橝C/

鈥橝CT163 has a Synchronous Reset input that overrides

counting and parallel loading and allows the outputs to be si-

multaneously reset on the rising edge of the clock.

Synchronous counting and loading

High-speed synchronous expansion

Typical count rate of 125 MHz

Outputs source/sink 24 mA

鈥橝CT163 has TTL-compatible inputs

Standard Microcircuit Drawing (SMD)

鈥?鈥橝C163: 5962-89582

鈥?鈥橝CT163: 5962-91723

Features

reduced by 50%

Logic Symbols

Names

CEP

CET

鈥揚(yáng)

鈥換

DS100275-1

Description

Count Enable Parallel Input

Count Enable Trickle Input

Clock Pulse Input

Synchronous Reset Input

Parallel Data Inputs

Parallel Enable Input

Flip-Flop Outputs

Terminal Count Output

IEEE/IEC

DS100275-2

FACT

鈩?/div>

is a trademark of Fairchild Semiconductor Corporation.

漏 1998 National Semiconductor Corporation

DS100275

www.national.com

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