鈥?/div>
54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The 鈥橝C/鈥橝CT109 consists of two high-speed completely in-
dependent transition clocked JK flip-flops. The clocking op-
eration is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to 鈥橝C/鈥橝CT74 data sheet) by connecting the J and K
inputs together.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n
n
n
n
I
CC
reduced by 50%
Outputs source/sink 24 mA
鈥橝CT109 has TTL-compatible inputs
Standard Military Drawing (SMD)
鈥?鈥橝C109: 5962-89551
鈥?鈥橝CT109: 5962-88534
Logic Symbol
IEEE/IEC
DS100267-1
DS100267-7
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
2
, Q
1
, Q
2
DS100267-2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100267
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