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54ABT652 Datasheet

  • 54ABT652

  • Octal Transceivers and Registers with TRI-STATE Outputs

  • 363.82KB

  • 17頁(yè)

  • NSC

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54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs
August 1998
54ABT652
Octal Transceivers and Registers with TRI-STATE
廬
Outputs
General Description
The 鈥橝BT652 consists of bus transceiver circuits with D-type
flip-flops, and control circuitry arranged for multiplexed trans-
mission of data directly from the input bus or from the inter-
nal registers. Data on the A or B bus will be clocked into the
registers as the appropriate clock pin goes to HIGH logic
level. Output Enable pins (OEAB, OEBA) are provided to
control the transceiver function.
n
Multiplexed real-time and stored data
n
A and B output sink capability of 48 mA, source
capability of 24 mA
n
Guaranteed latchup protection
n
High impedance glitch free bus loading during entire
power up and power down cycle
n
Nondestructive hot insertion capability
n
Standard Microcircuit Drawing (SMD) 5962-9324201
Features
n
Independent registers for A and B buses
Ordering Code:
Commercial
54ABT652J-QML
54ABT652W-QML
54ABT652E-QML
Package
Number
J24A
W24C
E28A
24-Lead Ceramic Dual-in-line
24-Lead Cerpack
28-Lead Ceramic Leadless Chip Carrier, Type C
Package Description
Connection Diagram
Pin Assignment for
DIP and Flatpack
DS100220-1
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100220
www.national.com

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