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4050B Datasheet

  • 4050B

  • Hex Inverting Buffer . Hex Non-Inverting Buffer

  • 7頁

  • FAIRCHILD

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CD4049UBC 鈥?CD4050BC Hex Inverting Buffer 鈥?Hex Non-Inverting Buffer
October 1987
Revised January 1999
CD4049UBC 鈥?CD4050BC
Hex Inverting Buffer 鈥?/div>
Hex Non-Inverting Buffer
General Description
The CD4049UBC and CD4050BC hex buffers are mono-
lithic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode
transistors. These devices feature logic level conversion
using only one supply voltage (V
DD
). The input signal high
level (V
IH
) can exceed the V
DD
supply voltage when these
devices are used for logic level conversions. These
devices are intended for use as hex buffers, CMOS to DTL/
TTL converters, or as CMOS current drivers, and at V
DD
=
5.0V, they can drive directly two DTL/TTL loads over the
full operating temperature range.
Features
s
Wide supply voltage range:
3.0V to 15V
s
Direct drive to 2 TTL loads at 5.0V over full temperature
range
s
High source and sink current capability
s
Special input protection permits input voltages greater
than V
DD
Applications
鈥?CMOS hex inverter/buffer
鈥?CMOS to DTL/TTL hex converter
鈥?CMOS current 鈥渟ink鈥?or 鈥渟ource鈥?driver
鈥?CMOS HIGH-to-LOW logic level converter
Ordering Code:
Order Number
CD4049UBCM
CD4049UBCN
CD4050BCM
CD4050BCN
Package Number
M16A
N16E
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150鈥?Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150鈥?Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagrams
Pin Assignments for DIP
CD4049UBC
CD4050BC
Top View
Top View
漏 1999 Fairchild Semiconductor Corporation
DS005971.prf
www.fairchildsemi.com

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