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403GCX-3BC50C2 Datasheet

  • 403GCX-3BC50C2

  • 32-Bit Microprocessor

  • 56頁(yè)

  • ETC

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PowerPC 403GCX
32-Bit RISC
Embedded Controller
Features
鈥?/div>
PowerPC
鈩?/div>
RISC CPU and instruction set
architecture
鈥?/div>
Glueless interfaces to DRAM, SRAM,
ROM, and peripherals, including byte and
half-word devices
鈥?/div>
16KB instruction cache and 8KB write-
back data cache, two-way set-associative
鈥?/div>
Memory management unit
鈥?4-entry, fully associative TLB array
鈥揤ariable page size (1KB-16MB)
鈥揊lexible TLB management
鈥?/div>
Individually programmable on-chip
controllers for:
鈥揊our DMA channels
鈥揇RAM, SRAM, and ROM banks
鈥揈xternal interrupts
鈥?/div>
DRAM controller supports EDO DRAM
鈥?/div>
Flexible interface to external bus masters
鈥?/div>
CPU core can run at 2X the external bus
speed
Applications
鈥?/div>
Set-top boxes and network computers
鈥?/div>
Consumer electronics and video games
鈥?/div>
Telecommunications and networking
鈥?/div>
Office automation (printers, copiers, fax)
Specifications
鈥?/div>
CPU core frequencies of 50, 66, and 80
MHz, I/Os to 25, 33, and 40 MHz
鈥?/div>
Interfaces to both 3V and 5V technologies
鈥?/div>
Low-power 3.3V operation with built-in
power management and stand-by mode
鈥?/div>
Low-cost 160 lead PQFP package
鈥?/div>
Small footprint 160 PBGA package
鈥?/div>
0.45
碌
m triple-level-metal CMOS
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Data
Sheet
Overview
The PowerPC 403GCX 32-bit RISC embedded
controller offers high performance and functional
integration with low power consumption. The
403GCX RISC CPU executes at sustained
speeds approaching one cycle per instruction.
On-chip caches and integrated DRAM and
SRAM control functions reduce chip count and
design complexity in systems, while improving
system throughput.
External I/O devices or SRAM/DRAM memory
banks can be directly attached to the 403GCX
bus interface unit (BIU). Interfaces for up to eight
memory banks and I/O devices, including a max-
imum of four DRAM banks, can be configured
individually, allowing the BIU to manage devices
or memory banks with differing control, timing, or
bus width requirements.
Interrupt
Controller
JTAG
Port
Serial
Port
4-Channel
DMA
Controller
(Address
and
Control)
Timers
RISC Execution Unit
Memory Management Unit
Instruction
Cache Unit
Data
Cache Unit
On-chip
Peripheral
Bus
Bus Interface Unit
DRAM Controller
I/O Controller
Data Address
Bus Bus
DRAM
Controls
SRAM, ROM, I/O
Controls

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