inc.
餂?/div>
3D7428Z-xx SOIC
IN
AE
SO/P0
P1
P2
P3
P4
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
P6
SC
P5
SI
3D7428-xx DIP
3D7428S-xx SOL
For mechanical dimensions, click
here.
For package marking details, click
here.
FUNCTIONAL DESCRIPTION
The 3D7428 device is a versatile 8-bit programmable monolithic delay
line. The input (IN) is reproduced at the output (OUT) without inversion,
shifted in time as per the user selection. Delay values, programmed
either via the serial or parallel interface, can be varied over 255 equal
steps according to the formula:
T
i,nom
= T
inh
+ i * T
inc
where i is the programmed address, T
inc
is the delay increment (equal
to the device dash number), and T
inh
is the inherent (address zero)
delay. The device features both rising- and falling-edge accuracy.
PIN DESCRIPTIONS
IN
OUT
MD
AE
P0-P7
SC
SI
SO
VDD
GND
Signal Input
Signal Output
Mode Select
Address Enable
Parallel Data Input
Serial Clock
Serial Data Input
Serial Data Output
+5 Volts
Ground
The all-CMOS 3D7428 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a surface mount
16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D7428-0.25
3D7428-0.5
3D7428-1
3D7428-1.5
3D7428-2
3D7428-2.5
3D7428-4
3D7428-5
3D7428-7.5
3D7428-10
3D7428-15
3D7428-20
DELAYS AND TOLERANCES
Inherent
Delay (ns)
10.5
鹵
2.0
10.5
鹵
2.0
10.5
鹵
2.0
10.5
鹵
2.0
10.5
鹵
2.0
10.5
鹵
2.5
13.0
鹵
4.0
15.0
鹵
5.0
20.0
鹵
7.5
23.5
鹵
10
33.0
鹵
15
42.0
鹵
20
Delay
Range (ns)
63.75
鹵
0.4
127.5
鹵
0.5
255.0
鹵
1.0
382.5
鹵
1.5
510.0
鹵
2.0
637.5
鹵
2.5
1020
鹵
3.2
1275
鹵
4.0
1912.5
鹵
6.0
2550
鹵
8.0
3825
鹵
12
5100
鹵
16
Delay
Step (ns)
0.25
鹵
0.12
0.50
鹵
0.25
1.00
鹵
0.50
1.50
鹵
0.75
2.00
鹵
1.00
2.50
鹵
1.25
4.00
鹵
2.00
5.00
鹵
2.50
7.50
鹵
3.75
10.0
鹵
5.00
15.0
鹵
9.00
20.0
鹵
12.0
Rec鈥檇 Max
Frequency
6.25 MHz
3.12 MHz
1.56 MHz
1.04 MHz
781 KHz
625 KHz
390 KHz
312 KHz
208 KHz
156 KHz
104 KHz
78 KHz
INPUT RESTRICTIONS
Absolute Max
Frequency
77 MHz
45 MHz
22 MHz
15 MHz
11 MHz
9.0 MHz
5.6 MHz
4.5 MHz
3.0 MHz
2.2 MHz
1.5 MHz
1.1 MHz
Rec鈥檇 Min
Pulse Width
80.0 ns
160.0 ns
320.0 ns
480.0 ns
640.0 ns
800.0 ns
1280.0 ns
1600.0 ns
2400.0 ns
3200.0 ns
4800.0 ns
6400.0 ns
Absolute Min
Pulse Width
6.5 ns
11.0 ns
22.0 ns
33.0 ns
44.0 ns
55.0 ns
88.0 ns
110.0 ns
165.0 ns
220.0 ns
330.0 ns
440.0 ns
NOTES: Any delay increment between 0.25 and 20 ns not shown is also available as standard.
See application notes section for more details
餂?004
Data Delay Devices
Doc #03003
11/1/04
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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