鈥?/div>
Operationally equivalent to Xilinx
廬
XC1700 family
Wide voltage range 3.0 V to 6.0 V
Maximum read current 10 mA at 5.0 V
Standby current 100
碌
A typical
Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock
Full Static Operation
Sequential Read/Program
Cascadable Output Enable
10 MHz Maximum Clock Rate @ 5.0 Vdc
Programmable Polarity on Hardware Reset
Programming with industry standard EPROM pro-
grammers
Electrostatic discharge protection > 4,000 volts
8-pin PDIP/SOIC and 20-pin PLCC packages
Data Retention > 200 years
Temperature ranges:
- Commercial: 0
擄
C to +70
擄
C
- Industrial:
-40
擄
C to +85
擄
C
PACKAGE TYPES
PDIP
DATA
CLK
RESET/OE
CE
1
8
V
CC
V
PP
CEO
V
SS
37LV36
37LV65
37LV128
2
3
4
7
6
5
SOIC
DATA
CLK
RESET/OE
CE
1
8
V
CC
V
PP
CEO
V
SS
37LV36
37LV65
37LV128
2
3
4
7
6
5
PLCC
DATA V
CC
3
2
1
20
12
19
18
17
V
PP
16
15
14
CEO
13
DESCRIPTION
The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter-
nally in a x32 con鏗乬uration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V V
CC
range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot-
strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.
Device
37LV36
37LV65
37LV128
Bits
36,288
65,536
131,072
Programming Word
1134 x 32
2048 x 32
4096 x 32
CLK
ADDRESS
Counter
CLK
4
5
37LV36
37LV65
37LV128
10
RESET/OE
6
7
CE
8
9
Vss
BLOCK DIAGRAM
CE
CEO
RESET/OE
11
EPROM
ARRAY
OE
DATA
Xilinx is a registered trademark of Xilinx Corporation.
漏
1996 Microchip Technology Inc.
DS21109E-page 1
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