鈥?/div>
to TTL, HTL, CMOS and Operational Amplifier Integrated Circuit
Logic Functions
Gate Triggering: 4 Mode 鈭?2N6071A, B; 2N6073A, B; 2N6075A, B
Blocking Voltages to 600 V
All Diffused and Glass Passivated Junctions for Greater Parameter
Uniformity and Stability
Small, Rugged, Thermopad Construction for Low Thermal
Resistance, High Heat Dissipation and Durability
Device Marking: Device Type, e.g., 2N6071A, Date Code
MT2
G
MT1
REAR VIEW
SHOW TAB
3
TO鈭?25
CASE 077
STYLE 5
2 1
MARKING DIAGRAM
YWW
2N
607xyG
= 1, 3, 5
= A, B
= Year
= Work Week
= Pb鈭扚ree Package
1. Cathode
2. Anode
3. Gate
x
y
Y
WW
G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Preferred
devices are recommended choices for future use
and best overall value.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
1
April, 2006 鈭?Rev. 7
Publication Order Number:
2N6071/D