鈩?/div>
Bus Serial EEPROM
PACKAGE TYPES
Temp
Ranges
C,I,E
C,I
PDIP, SOIC
CS
SO
WP
V
SS
1
25xx320
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
Max Clock
Frequency
3 MHz
2 MHz
DEVICE SELECTION TABLE
FEATURES
鈥?Low power CMOS technology
- Write current: 3 mA maximum
- Read current: 500
碌A(chǔ)
typical
- Standby current: 500 nA typical
鈥?4096 x 8 bit organization
鈥?32 byte page
鈥?Write cycle time: 5ms max.
鈥?Self-timed ERASE and WRITE cycles
鈥?Block write protection
- Protect none, 1/4, 1/2, or all of array
鈥?Built-in write protection
- Power on/off data protection circuitry
- Write enable latch
- Write protect pin
鈥?Sequential read
鈥?High reliability
- Endurance: 1M cycles (guaranteed)
- Data retention: > 200 years
- ESD protection: > 4000 V
鈥?8-pin PDIP, SOIC, and 14 lead TSSOP packages
鈥?Temperature ranges supported:
- Commercial (C):
0擄C to +70擄C
- Industrial (I):
-40擄C to +85擄C
- Automotive (E) (25C320):
-40擄C to +125擄C
TSSOP
CS 1
SO 2
NC 3
NC 4
NC 5
WP 6
V
SS
7
14 V
CC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
25xx320
BLOCK DIAGRAM
Status
Register
HV Generator
EEPROM
I/O Control
Logic
Memory
Control
Logic
X
Dec
Page Latches
Array
DESCRIPTION
The Microchip Technology Inc. 25LC320/25C320
(25xx320
*
) are 32K bit serial Electrically Erasable
PROMs. The memory is accessed via a simple Serial
Peripheral Interface (SPI) compatible serial bus. The
bus signals required are a clock input (SCK) plus sep-
arate data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts.
SI
SO
CS
SCK
HOLD
WP
V
CC
V
SS
Y Decoder
Sense Amp.
R/W Control
*25xx320 is used in this document as a generic part number for the 25LC320/25C320 devices.
SPI is a trademark of Motorola.
漏
1998 Microchip Technology Inc.
DS21227B-page 1