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24C65-SM Datasheet

  • 24C65-SM

  • 64K 5.0V I 2 C Smart Serial EEPROM

  • 16頁

  • MICROCHIP   MICROCHIP

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24C65
64K 5.0V I
2
C
鈩?/div>
Smart Serial
鈩?/div>
EEPROM
FEATURES
鈥?Voltage operating range: 4.5V to 5.5V
- Peak write current 3 mA at 5.5V
- Maximum read current 150
碌
A at 5.5V
- Standby current 1
碌
A typical
鈥?Industry standard two-wire bus protocol, I
2
C
鈩?/div>
compatible
鈥?8 byte page, or byte modes available
鈥?2 ms typical write cycle time, byte or page
鈥?64-byte input cache for fast write loads
鈥?Up to eight devices may be connected to the
same bus for up to 512K bits total memory
鈥?Including 400 KHz compatibility
鈥?Programmable block security options
鈥?Programmable endurance options
鈥?Schmitt trigger, 鏗乴tered inputs for noise suppres-
sion
鈥?Output slope control to eliminate ground bounce
鈥?Self-timed ERASE and WRITE cycles
鈥?Power on/off data protection circuitry
鈥?Endurance:
- 10,000,000 E/W cycles guaranteed for High
Endurance Block
- 100,000 E/W cycles guaranteed for a Stan-
dard Endurance Block
鈥?Electrostatic discharge protection > 4000V
鈥?Data retention > 200 years
鈥?8-pin PDIP/SOIC packages
鈥?Temperature ranges
- Commercial (C):
0
擄
C to +70
擄
C
- Industrial (I)
-40
擄
C to +85
擄
C
- Automotive (E):
-40
擄
C to +125
擄
C
PACKAGE TYPES
PDIP
A0
A1
A2
V
SS
1
2
3
4
24C65
8
7
6
5
V
CC
NC
SCL
SDA
SOIC
A0
A1
A2
V
SS
1
2
3
4
24C65
8
7
6
9
V
CC
NC
SCL
SDA
BLOCK DIAGRAM
A0..A2
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM ARRAY
Page Latches
Cache
DESCRIPTION
The Microchip Technology Inc. 24C65 is a 鈥渟mart鈥?8K x
8 Serial Electrically Erasable PROM (EEPROM). This
device has been developed for advanced, low power
applications such as personal communications, and
provides the systems designer with 鏗俥xibility through
the use of many new user-programmable features. The
24C65 offers a relocatable 4K bit block of
ultra-high-endurance memory for data that changes
frequently. The remainder of the array, or 60K bits, is
rated at 1,000,000 ERASE/WRITE (E/W) cycles guar-
anteed. The 24C65 features an input cache for fast
write loads with a capacity of eight pages, or 64 bytes.
This device also features programmable security
I/O
SCL
YDEC
SDA
Vcc
Vss
Sense AMP
R/W Control
options for E/W protection of critical data and/or code of
up to 鏗乫teen 4K blocks. Functional address lines allow
the connection of up to eight 24C65's on the same bus
for up to 512K bits contiguous EEPROM memory.
Advanced CMOS technology makes this device ideal
for low-power nonvolatile code and data applications.
The 24C65 is available in the standard 8-pin plastic DIP
and 8-pin surface mount SOIC package.
I
2
C is a trademark of Philips Corporation.
Smart Serial is a trademark of Microchip Technology Inc.
漏
1996 Microchip Technology Inc.
DS21058G-page 1
This document was created with FrameMaker 4 0 4

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