鈩?/div>
compatible
鈥?100 kHz and 400 kHz compatibility
鈥?Self-timed ERASE and WRITE cycles
鈥?Power on/off data protection circuitry
鈥?Hardware write protect
鈥?1,000,000 Erase/Write cycles guaranteed
鈥?32-byte page or byte write modes available
鈥?Schmitt trigger 鏗乴tered inputs for noise suppres-
sion
鈥?Output slope control to eliminate ground bounce
鈥?2 ms typical write cycle time, byte or page
鈥?Up to eight devices may be connected to the
same bus for up to 256K bits total memory
鈥?Electrostatic discharge protection > 4000V
鈥?Data retention > 200 years
鈥?8-pin PDIP and SOIC packages
鈥?Temperature ranges
- Commercial (C):
0藲C to
70藲C
- Industrial (I):
-40藲C to +85藲C
- Automotive (E):
-40藲C to +125藲C
PACKAGE TYPES
PDIP
A0
A1
A2
Vss
1
24C32A
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
SOIC
A0
A1
A2
Vss
1
24C32A
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
DESCRIPTION
The Microchip Technology Inc. 24C32A is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM. It has been
developed for advanced, low power applications such
as personal communications or data acquisition. The
24C32A also has a page-write capability of up to 32
bytes of data. The 24C32A is capable of both random
and sequential reads up to the 32K boundary. Func-
tional address lines allow up to eight 24C32A devices
on the same bus, for up to 256K bits address space.
Advanced CMOS technology and broad voltage range
make this device ideal for low-power/low-voltage, non-
volatile code and data applications. The 24C32A is
available in the standard 8-pin plastic DIP and both 150
mil and 200 mil SOIC packaging.
BLOCK DIAGRAM
A0..A2
WP
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
I/O
SCL
YDEC
SDA
V
CC
V
SS
SENSE AMP
R/W CONTROL
I
2
C is a trademark of Philips Corporation.
漏
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21163B-page 1