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24C320-ST Datasheet

  • 24C320-ST

  • 32K 5.0V SPI Bus Serial EEPROM

  • 12頁

  • MICROCHIP   MICROCHIP

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25C320
32K 5.0V SPI
鈩?/div>
Bus Serial EEPROM
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
SPI modes 0,0 and 1,1
3.0 MHz Clock Rate
Single 5V Supply
Low Power CMOS Technology
- Max Write Current: 5 mA
- Read Current: 1.0 mA at 5.5V, 3MHz
- Standby Current: 1
碌
A typical
4096 x 8 Organization
32 Byte Page
Sequential Read
Self-timed ERASE and WRITE Cycles
Block Write Protection
- Protect none, 1/4, 1/2, or all of Array
Built-in Write Protection
- Power On/Off Data Protection Circuitry
- Write Enable Latch
- Write Protect Pin
High Reliability
- Endurance: 1M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000V
8-pin PDIP/SOIC, 14-pin TSSOP
Temperature ranges supported
- Commercial (C):
0
擄
C to +70
擄
C
- Industrial (I):
-40
擄
C to +85
擄
C
- Automotive (E):
-40
擄
C to +125
擄
C
PACKAGE TYPES
DIP/SOIC
CS
SO
WP
V
SS
1
25C320
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
TSSOP
CS 1
SO 2
NC 3
NC 4
NC 5
WP 6
V
SS
7
14 V
CC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
25C320
鈥?/div>
BLOCK DIAGRAM
Status
Register
HV Generator
鈥?/div>
鈥?/div>
EEPROM
I/O Control
Logic
Memory
Control
Logic
X
Dec
Page Latches
WP
SI
SO
CS
SCK
HOLD
Sense Amp.
R/W Control
Y Decoder
Array
DESCRIPTION
The Microchip Technology Inc. 25C320 is a 32K-bit
serial Electrically Erasable PROM (EEPROM). The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
There are two other inputs that provide the end user
with additional 鏗俥xibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also write
operations to the Status Register can be disabled via
the write protect pin (WP).
Vcc
Vss
SPI is a trademark of Motorola.
漏
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21159B-page 1

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