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100398QI Datasheet

  • 100398QI

  • Quad Differential ECL/TTL Translating Transceiver with Latch

  • 13頁(yè)

  • FAIRCHILD

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100398 Quad Differential ECL/TTL Translating Transceiver with Latch
February 1992
Revised August 2000
100398
Quad Differential ECL/TTL Translating Transceiver
with Latch
General Description
The 100398 is a quad latched transceiver designed to con-
vert TTL logic levels to differential F100K ECL logic levels
and vice versa. This device was designed with the capabil-
ity of driving a differential 25
鈩?/div>
ECL load with cutoff capabil-
ity, and will sink a 64 mA TTL load. The 100398 is ideal for
mixed technology applications utilizing either an ECL or
TTL backplane.
The direction of translation is set by the direction control
pin (DIR). The DIR pin on the 100398 accepts TTL logic
levels. A TTL LOW on DIR sets up the ECL pins as inputs
and TTL pins as outputs. A TTL HIGH on DIR sets up the
TTL pins as inputs and ECL pins as outputs.
A LOW on the output enable input pin (OE) holds the ECL
output in a cut-off state and the TTL outputs at a high
impedance level. A HIGH on the latch enable input (LE)
latches the data at both inputs even though only one output
is enabled at the time. A LOW on LE makes the latch trans-
parent.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is
鈭?/div>
2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces termination power and prevents loss of
low state noise margin when several loads share the bus.
The 100398 is designed with FAST
錚?/div>
TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All Inputs have
50 k
鈩?/div>
pull-down resistors.
Features
s
Differential ECL input/output structure
s
64 mA FAST TTL outputs
s
25
鈩?/div>
differential ECL outputs with cut-off
s
Bi-directional translation
s
2000V ESD protection
s
Latched outputs
s
3-STATE outputs
s
Voltage compensated operating range
= 鈭?/div>
4.2V to
鈭?/div>
5.7V
Ordering Code:
Order Number
100398PC
100398QC
100398QI
Package Number
N24E
V28A
V28A
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
鈭?/div>
40
擄
C to
+
85
擄
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
FAST錚?is a registered trademark of Fairchild Semiconductor.
漏 2000 Fairchild Semiconductor Corporation
DS010970
www.fairchildsemi.com

100398QI 產(chǎn)品屬性

  • Fairchild Semiconductor

  • ECL

  • ECL

  • 4

  • TTL

  • ECL

  • 3-State

  • - 3 mA

  • 24 mA

  • 5.1 ns

  • - 5.7 V, + 5.5 V

  • - 4.2 V, + 4.5 V

  • + 85 C

  • PLCC-28

  • Rail

  • Latched Transceiver

  • - 40 C

  • SMD/SMT

  • 1

  • Inverting, Non-Inverting

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