鈩?/div>
. To reduce crosstalk, each output has its own
respective ground connection. Transition times were
designed to be longer than on other F100K devices. The
driver itself performs the positive logic AND of a data input
(D
1
鈥揇
6
) and the OR of two select inputs (E and either DE
1
,
DE
2
, or DE
3
).
Enabling of data is possible in multiples of two, i.e., 2, 4 or
all 6 paths. All inputs have 50 k
鈩?/div>
pull-down resistors.
The output voltage LOW level is designed to be more neg-
ative than normal ECL outputs (cut off state). This allows
an emitter-follower output transistor to turn OFF when the
termination supply is
鈭?/div>
2.0V and thus present a high imped-
ance to the data bus.
Features
s
50% power reduction of the 100123
s
2000V ESD protection
s
鈭?/div>
4.2V to
鈭?/div>
5.7V operating range
s
Drives 25
鈩?/div>
load
Ordering Code:
Order Number
100323PC
100323QC
Package Number
N24E
V28A
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
D
1
鈥揇
6
DE
1
鈥揇E
3
E
O
1
鈥揙
6
Data Inputs
Dual Enable Inputs
Common Enable Input
Data Outputs
28-Pin PLCC
Description
漏 2000 Fairchild Semiconductor Corporation
DS009877
www.fairchildsemi.com
100323QC相關型號PDF文件下載
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1
2
3
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5
6
