FDG6318P
January 2003
FDG6318P
Dual P-Channel, Digital FET
General Description
These dual P-Channel logic level enhancement mode
MOSFET are produced using Fairchild Semiconductor鈥檚
advanced PowerTrench process that has been
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage
applications as a replacement for bipolar digital
transistors and small signal MOSFETS.
Features
鈥?/div>
鈥?.5 A, 鈥?0 V.
R
DS(ON)
= 780 m鈩?@ V
GS
= 鈥?.5 V
R
DS(ON)
= 1200 m鈩?@ V
GS
= 鈥?.5 V
鈥?/div>
Very low level gate drive requirements allowing direct
operation in 3V circuits (V
GS(th)
< 1.5V).
鈥?/div>
Compact industry standard SC70-6 surface mount
package
Applications
鈥?/div>
Battery management
S
G
D
D
G
Pin 1
S
1 or 4
6 or 3
D
5 or 2
G
4 or 1
S
G
2 or 5
S
D
3 or 6
SC70-6
The pinouts are symmetrical; pin 1 and pin 4 are interchangeable.
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
, T
STG
Drain-Source Voltage
Gate-Source Voltage
Drain Current
鈥?Continuous
鈥?Pulsed
T
A
=25 C unless otherwise noted
o
Parameter
Ratings
鈥?0
鹵12
(Note 1)
Units
V
V
A
W
擄C
鈥?.5
鈥?.8
0.3
鈥?5 to +150
Power Dissipation for Single Operation
(Note 1)
Operating and Storage Junction Temperature Range
Thermal Characteristics
R
胃JA
Thermal Resistance, Junction-to-Ambient
(Note 1)
415
擄C/W
Package Marking and Ordering Information
Device Marking
.38
Device
FDG6318P
Reel Size
7鈥欌€?/div>
Tape width
8mm
Quantity
3000 units
餂?003
Fairchild Semiconductor Corporation
FDG6318P Rev C (W)
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